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ISD2532/40/48/64
SINGLE-CHIP, MULTIPLE-MESSAGES, VOICE RECORD/PLAYBACK DEVICE 32-, 40-, 48-, AND 64-SECOND DURATION
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
1. GENERAL DESCRIPTION
Winbond's ISD2500 ChipCorder(R) Series provide high-quality, single-chip, Record/Playback solutions for 32- to 64-second messaging applications. The CMOS devices include an on-chip oscillator, microphone preamplifier, automatic gain control, antialiasing filter, smoothing filter, speaker amplifier, and high density multi-level storage array. In addition, the ISD2500 is microcontroller compatible, allowing complex messaging and addressing to be achieved. Recordings are stored into on-chip nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is made possible through Winbond's patented multilevel storage technology. Voice and audio signals are stored directly into memory in their natural form, providing high-quality, solid-state voice reproduction.
2. FEATURES
* * * * * * * *
Single 5 volt power supply Single-chip with duration of 32, 40, 48, or 64 seconds. Easy-to-use single-chip, voice record/playback solution High-quality, natural voice/audio reproduction Manual switch or microcontroller compatible Playback can be edge- or level-activated Directly cascadable for longer durations Automatic power-down (push-button mode) - Standby current 1 A (typical) Zero-power message storage - Eliminates battery backup circuits Fully addressable to handle multiple messages 100-year message retention (typical) 100,000 record cycles (typical) On-chip clock source Programmer support for play-only applications Available in die form, PDIP, SOIC and TSOP packaging Temperature options: die (0C to +50C) and package (0C to +70C)
*
* * * * * * *
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3. BLOCK DIAGRAM
Internal Clock XCLK
Timing
Sampling Clock ANA IN Amp 5-Pole Active Antialiasing Filter Decoders Analog Transceivers 256K Cell Nonvolatile Multilevel Storage Array
ANA OUT MIC MIC REF AGC PreAmp Automatic Gain Control (AGC) Power Conditioning
5-Pole Active Smoothing Filter SP +
Mux
Amp SP -
Address Buffers
Device Control
VCCA
VSSA VSSD VCCD
A0 A1 A2 A3 A4 A5 A6 A7 A8
PD
OVF
P/R
CE
EOM
AUX IN
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4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 5 6. PIN DESCRIPTION ............................................................................................................................. 6 7. FUNCTIONAL DESCRIPTION.......................................................................................................... 10 7.1. Detailed Description.................................................................................................................... 10 7.2. Operational Modes ..................................................................................................................... 11 7.2.1. Operational Modes Description............................................................................................ 12 8. TIMING DIAGRAMS.......................................................................................................................... 16 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 19 9.1 Operating Conditions ................................................................................................................... 20 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21 10.1. Parameters For Packaged Parts .............................................................................................. 21 10.1.1. Typical Parameter Variation with Voltage and Temperature - Packaged Parts ................ 24 10.2. Parameters For Die .................................................................................................................. 25 10.2.1. Typical Parameter Variation with Voltage and Temperature - Die .................................... 28 10.3. Parameters For Push-Button Mode.......................................................................................... 29 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 30 12. PACKAGE DRAWING AND DIMENSIONS .................................................................................... 35 12.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC)..................................................................... 35 12.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) ............................................................... 36 12.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 ................................ 37 12.4. Die Bonding Physical Layout [1] ................................................................................................ 38 14. VERSION HISTORY ....................................................................................................................... 41
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5. PIN CONFIGURATION
A0/M 0 A1/M 1 A2/M 2 A3/M 3 A4/M 4 A5/M 5 A6/M 6 NC A7 A8 AUX IN V SSD V SSA SP +
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
V CCD P/R XCLK EOM PD CE OVF ANA OUT ANA IN AGC M IC REF M IC V CCA SP-
ISD2532 ISD2540 ISD2548 ISD2564
23 22 21 20 19 18 17 16 15
SOIC/PDIP
OVF CE PD EOM XCLK P/R V CCD A0/M 0 A1/M 1 A2/M 2 A3/M 3 A4M 4 A5/M 5 A6/M 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25
ISD2532 ISD2340 ISD2548 ISD2564
24 23 22 21 20 19 18 17 16 15
ANA OUT ANA IN AGC M IC REF M IC V CCA SPSP+ V SSA V SSD AUX IN A8 A7 NC
TSOP
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6. PIN DESCRIPTION
PIN NO. PIN NAME A0, A1, A2, A3, A4, A5, A6, A7, A8 / M0, M1, M2, M3, M4, M5, M6 SOIC / PDIP TSOP FUNCTION
1, 2, 3, 8, 9, 10, Address/Mode Inputs: The Address/Mode Inputs have two functions 4, 5, 6, 11, 12, 13, depending on the level of the two Most Significant Bits (MSB) of the 7, 9, 10 14, 16, 17 address pins A7 and A8. / 1, 2, 3, 4, 5, 6, 7 / 8, 9, 10, 11, 12, 13, 14 If either or both of the two MSBs are LOW, the inputs are all interpreted as address bits and are used as the start address for the current record or playback cycle. The address pins are inputs only and do not output any internal address information during the operation. Address inputs are latched by the falling edge of CE . If both MSBs are HIGH, the Address/Mode inputs are interpreted as Mode bits according to the Operational Mode table on page 12. There are six operational modes (M0...M6) available as indicated in the table. It is possible to use multiple operational modes simultaneously. Operational Modes are sampled on each falling edge of CE , and thus Operational Modes and direct addressing are mutually exclusive.
NC AUX IN
8 11
15 18
No Connect. Auxiliary Input: The Auxiliary Input is multiplexed through to the output amplifier and speaker output pins when CE is HIGH, P/ R is HIGH, and playback is currently not active or if the device is in playback overflow. When cascading multiple ISD2500 devices, the AUX IN pin is used to connect a playback signal from a following device to the previous output speaker drivers. For noise considerations, it is suggested that the auxiliary input not be driven when the storage array is active.
VSSA, VSSD
13, 12
20, 19
Ground: The ISD2500 series of devices utilizes separate analog and digital ground busses. These pins should be connected separately through a low-impedance path to power supply ground. Speaker Outputs: All devices in the ISD2500 series include an on-chip differential speaker driver, capable of driving 50 mW into 16 from AUX IN (12.2mW from memory).
[1]
SP+, SP-
14, 15
21, 22
The speaker outputs are held at VSSA levels during record and power down. It is therefore not possible to parallel speaker outputs of multiple ISD2500 devices or the outputs of other speaker drivers.
[2]
A single-end output may be used (including a coupling capacitor between the SP pin and the speaker). These outputs may be used individually with the output signal taken from either pin. However, the use of single-end output results in a 1 to 4 reduction in its output power.
[1] [2]
Connection of speaker outputs in parallel may cause damage to the device. Never ground or drive an unused speaker output.
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PIN NO. PIN NAME VCCA, VCCD SOIC/ PDIP 16, 28 TSOP 23, 7 FUNCTION Supply Voltage: To minimize noise, the analog and digital circuits in the ISD2500 series devices use separate power busses. These voltage busses are brought out to separate pins and should be tied together as close to the supply as possible. In addition, these supplies should be decoupled as close to the package as possible. Microphone: The microphone pin transfers input signal to the onchip preamplifier. A built-in Automatic Gain Control (AGC) circuit controls the gain of this preamplifier from -15 to 24dB. An external microphone should be AC coupled to this pin via a series capacitor. The capacitor value, together with the internal 10 K resistance on this pin, determines the low-frequency cutoff for the ISD2500 series passband. See Winbond's Application Information for additional information on low-frequency cutoff calculation. Microphone Reference: The MIC REF input is the inverting input to the microphone preamplifier. This provides a noise-canceling or common-mode rejection input to the device when connected to a differential microphone. Automatic Gain Control: The AGC dynamically adjusts the gain of the preamplifier to compensate for the wide range of microphone input levels. The AGC allows the full range of whispers to loud sounds to be recorded with minimal distortion. The "attack" time is determined by the time constant of a 5 K internal resistance and an external capacitor (C2 on the schematic of Figure 5 in section 11) connected from the AGC pin to VSSA analog ground. The "release" time is determined by the time constant of an external resistor (R2) and an external capacitor (C2) connected in parallel between the AGC pin and VSSA analog ground. Nominal values of 470 K and 4.7 F give satisfactory results in most cases. Analog Input: The analog input transfers analog signal to the chip for recording. For microphone inputs, the ANA OUT pin should be connected via an external capacitor to the ANA IN pin. This capacitor value, together with the 3.0 K input impedance of ANA IN, is selected to give additional cutoff at the low-frequency end of the voice passband. If the desired input is derived from a source other than a microphone, the signal can be fed, capacitively coupled, into the ANA IN pin directly.
MIC
17
24
MIC REF
18
25
AGC
19
26
ANA IN
20
27
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PIN NO. PIN NAME ANA OUT SOIC/ PDIP 21 TSOP 28 FUNCTION Analog Output: This pin provides the preamplifier output to the user. The voltage gain of the preamplifier is determined by the voltage level at the AGC pin. Overflow: This signal pulses LOW at the end of memory array, indicating the device has been filled and the message has overflowed. The OVF output then follows the CE input until a PD pulse has reset the device. This pin can be used to cascade several ISD2500 devices together to increase record/playback durations.
CE
OVF
22
1
23
2
Chip Enable: The CE input pin is taken LOW to enable all playback and record operations. The address pins and playback/record pin (P/ R ) are latched by the falling edge of CE .
CE has additional functionality in the M6 (Push-Button) Operational Mode as described in the Operational Mode section.
PD
24
3
Power Down: When neither record nor playback operation, the PD pin should be pulled HIGH to place the part in standby mode (see ISB specification). When overflow ( OVF ) pulses LOW for an overflow condition, PD should be brought HIGH to reset the address pointer back to the beginning of the memory array. The PD pin has additional functionality in the M6 (Push-Button) Operation Mode as described in the Operational Mode section.
EOM
25
4
End-Of-Message: A nonvolatile marker is automatically inserted at the end of each recorded message. It remains there until the message is recorded over. The EOM output pulses LOW for a period of TEOM at the end of each message. In addition, the ISD2500 series has an internal VCC detect circuit to maintain message integrity should VCC fall below 3.5V. In this case,
EOM goes LOW and the device is fixed in Playback-only mode.
When the device is configured in Operational Mode M6 (PushButton Mode), this pin provides an active-HIGH signal, indicating the device is currently recording or playing. This signal can conveniently drive an LED for visual indicator of a record or playback operation in process.
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PIN NO. PIN NAME XCLK SOIC/ PDIP 26 TSOP 5 FUNCTION External Clock: The external clock input has an internal pull-down device. The device is configured at the factory with an internal sampling clock frequency centered to 1 percent of specification. The frequency is then maintained to a variation of 2.25 percent over the entire commercial temperature and operating voltage ranges. If greater precision is required, the device can be clocked through the XCLK pin as follows:
Part Number ISD2532 ISD2540 ISD2548 ISD2564 Sample Rate 8.0 kHz 6.4 kHz 5.3 kHz 4.0 kHz Required Clock 1024 kHz 819.2 kHz 682.7 kHz 512 kHz
These recommended clock rates should not be varied because the antialiasing and smoothing filters are fixed, and aliasing problems can occur if the sample rate differs from the one recommended. The duty cycle on the input clock is not critical, as the clock is immediately divided by two. If the XCLK is not used, this input must be connected to ground. P/ R 27 6 Playback/Record: The P/ R input pin is latched by the falling edge of the CE pin. A HIGH level selects a playback cycle while a LOW level selects a record cycle. For a record cycle, the address pins provide the starting address and recording continues until PD or
CE is pulled HIGH or an overflow is detected (i.e. the chip is full).
When a record cycle is terminated by pulling PD or CE HIGH, then End-Of-Message ( EOM ) marker is stored at the current address in memory. For a playback cycle, the address inputs provide the starting address and the device will play until an EOM marker is encountered. The device can continue to pass an EOM marker if CE is held LOW in address mode, or in an Operational Mode. (See Operational Modes section)
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7. FUNCTIONAL DESCRIPTION
7.1. DETAILED DESCRIPTION
Speech/Sound Quality The Winbond's ISD2500 series includes devices offered at 4.0, 5.3, 6.4, and 8.0 kHz sampling frequencies, allowing the user a choice of speech quality options. Increasing the duration within a product series decreases the sampling frequency and bandwidth, which affects the sound quality. Please refer to the ISD2532/40/48/64 Product Summary table below to compare the duration, sampling frequency and filter pass band. The speech samples are stored directly into the on-chip nonvolatile memory without any digitization and compression associated like other solutions. Direct analog storage provides a very true, natural sounding reproduction of voice, music, tones, and sound effects not available with most solid state digital solutions.
Duration To meet various system requirements, the ISD2532/40/48/64 products offer single-chip solutions at 32, 40, 48, and 64 seconds. Parts may also be cascaded together for longer durations. TABLE 1: ISD2532/40/48/64 PRODUCT SUMMARY Part Number ISD2532 ISD2540 ISD2548 ISD2564
*
Duration (Seconds) 32 40 48 64
Input Sample Rate (kHz) 8.0 6.4 5.3 4.0
Typical Filter Pass Band * (kHz) 3.4 2.7 2.3 1.7
3dB roll off point. This parameter is not checked during production testing and may vary due to process variations and other factors. Therefore, customer should not rely on this value for testing purposes.
EEPROM Storage One of the benefits of Winbond's ChipCorder(R) technology is the use of on-chip nonvolatile memory, providing zero-power message storage. The message is retained for up to 100 years typically without power. In addition, the device can be re-recorded typically over 100,000 times. Microcontroller Interface In addition to its simplicity and ease of use, the ISD2500 series includes all the interfaces necessary for microcontroller-driven applications. The address and control lines can be interfaced to a microcontroller and manipulated to perform a variety of tasks, including message assembly, message concatenation, predefined fixed message segmentation, and message management.
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Programming The ISD2500 series is also ideal for playback-only applications, where single or multiple messages are referenced through buttons, switches, or a microcontroller. Once the desired message configuration is created, duplicates can easily be generated via a gang programmer.
7.2. OPERATIONAL MODES
The ISD2500 series is designed with several built-in Operational Modes that provide maximum functionality with minimum external components. These modes are described in details as below. The Operational Modes are accessed via the address pins and mapped beyond the normal message address range. When the two Most Significant Bits (MSB), A7 and A8, are HIGH, the remaining address signals are interpreted as mode bits and not as address bits. Therefore, Operational Modes and direct addressing are not compatible and cannot be used simultaneously. There are two important considerations for using Operational Modes. First, all operations begin initially at address 0 of its memory. Later operations can begin at other address locations, depending on the Operational Mode(s) chosen. In addition, the address pointer is reset to 0 when the device is changed from record to playback, playback to record (except M6 mode), or when a Power-Down cycle is executed. Second, Operational Modes are executed when CE goes LOW. This Operational Mode remains in effect until the next LOW-going CE signal, at which point the current mode(s) are sampled and executed. TABLE 2: OPERATIONAL MODES Mode M0 M1 M2 M3 M4 M5 M6
[1]
Function Message cueing Delete EOM markers Not applicable Looping Consecutive addressing
CE level-activated
Typical Use Fast-forward through messages Position EOM marker at the end of the last message Reserved Continuous playback from Address 0 Record/playback multiple consecutive messages Allows message pausing Simplified device interface
Jointly Compatible [2] M4, M5, M6 M3, M4, M5, M6 N/A M1, M5, M6 M0, M1, M5 M0, M1, M3, M4 M0, M1, M3
Push-button control
[1]
Besides mode pin needed to be "1", A7 and A8 pin are also required to be "1" in order to enter into the related operational mode. Indicates additional Operational Modes which can be used simultaneously with the given mode.
[2]
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7.2.1. Operational Modes Description The Operational Modes can be used in conjunction with a microcontroller, or they can be hardwired to provide the desired system operation.
M0 - Message Cueing Message Cueing allows the user to skip through messages, without knowing the actual physical addresses of each message. Each CE LOW pulse causes the internal address pointer to skip to the next message. This mode is used for playback only, and is typically used with the M4 Operational Mode.
M1 - Delete EOM Markers The M1 Operational Mode allows sequentially recorded messages to be combined into a single message with only one EOM marker set at the end of the final message. When this Operational Mode is configured, messages recorded sequentially are played back as one continuous message. M2 - Unused When Operational Modes are selected, the M2 pin should be LOW. M3 - Message Looping The M3 Operational Mode allows for the automatic, continuously repeated playback of the message located at the beginning of the address space. A message can completely fill the ISD2500 device and will loop from beginning to end without OVF going LOW. M4 - Consecutive Addressing During normal operation, the address pointer will reset when a message is played through an EOM marker. The M4 Operational Mode inhibits the address pointer reset on EOM , allowing messages to be played back consecutively.
M5 - CE -Level Activated The default mode for ISD2500 devices is for CE to be edge-activated on playback and levelactivated on record. The M5 Operational Mode causes the CE pin to be interpreted as levelactivated as opposed to edge-activated during playback. This is especially useful for terminating playback operations using the CE signal. In this mode, CE LOW begins a playback cycle, at the beginning of the device memory. The playback cycle continues as long as CE is held LOW. When
CE goes HIGH, playback will immediately end. A new CE LOW will restart the message from the beginning unless M4 is also HIGH.
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M6 - Push-Button Mode The ISD2500 series contain a Push-Button Operational Mode. The Push-Button Mode is used primarily in very low-cost applications and is designed to minimize external circuitry and components, thereby reducing system cost. In order to configure the device in Push-Button Operational Mode, the two most significant address bits must be HIGH, and the M6 mode pin must also be HIGH. A device in this mode always powers down at the end of each playback or record cycle after CE goes HIGH. When this operational mode is implemented, three of the pins on the device have alternate functionality as described in the table below. TABLE 3: ALTERNATE FUNCTIONALITY IN PINS Pin Name
CE
Alternate Functionality in Push-Button Mode Start/Pause Push-Button (LOW pulse-activated) Stop/Reset Push-Button (HIGH pulse-activated) Active-HIGH Run Indicator
PD
EOM
CE (START/PAUSE)
In Push-Button Operational Mode, CE acts as a LOW-going pulse-activated START/PAUSE signal. If no operation is currently in progress, a LOW-going pulse on this signal will initiate a playback or record cycle according to the level on the P/ R pin. A subsequent pulse on the CE pin, before an
EOM is reached in playback or an overflow condition occurs, will pause the current operation, and
the address counter is not reset. Another CE pulse will cause the device to continue the operation from the place where it is paused. PD (STOP/RESET) In Push-Button Operational Mode, PD acts as a HIGH-going pulse-activated STOP/RESET signal. When a playback or record cycle is in progress and a HIGH-going pulse is observed on PD, the current cycle is terminated and the address pointer is reset to address 0, the beginning of the message space.
EOM (RUN)
In Push-Button Operational Mode, EOM becomes an active-HIGH RUN signal which can be used to drive an LED or other external device. It is HIGH whenever a record or playback operation is in progress. Recording in Push-Button Mode 1. The PD pin should be LOW, usually using a pull-down resistor. Publication Release Date: June 2003 Revision 1.0
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2. The P/ R pin is taken LOW. 3. The CE pin is pulsed LOW. Recording starts, EOM goes HIGH to indicate an operation in progress. 4. When the CE pin is pulsed LOW. Recording pauses, EOM goes back LOW. The internal address pointers are not cleared, but the EOM marker is stored in memory to indicate as the message end. The P/ R pin may be taken HIGH at this time. Any subsequent CE would start a playback at address 0. 5. The CE pin is pulsed LOW. Recording starts at the next address after the previous set
EOM marker. EOM goes back HIGH.[3]
6. When the recording sequences are finished, the final CE pulse LOW will end the last record cycle, leaving a set EOM marker at the message end. Recording may also be terminated by a HIGH level on PD, which will leave a set EOM marker. Playback in Push-Button Mode 1. The PD pin should be LOW. 2. The P/ R pin is taken HIGH. 3. The CE pin is pulsed LOW. Playback starts, EOM goes HIGH to indicate an operation in progress. 4. If the CE pin is pulsed LOW or an EOM marker is encountered during an operation, the part will pause. The internal address pointers are not cleared, and EOM goes back LOW. The P/ R pin may be changed at this time. A subsequent record operation would not reset the address pointers and the recording would begin where playback ended. 5.
CE is again pulsed LOW. Playback starts where it left off, with EOM going HIGH to indicate an operation in progress.
6. Playback continues as in steps 4 and 5 until PD is pulsed HIGH or overflow occurs. 7. If in overflow, pulling CE LOW will reset the address pointer and start playback from the beginning. After a PD pulse, the part is reset to address 0.
Note: Push-Button Mode can be used in conjunction with modes M0, M1, and M3.
[3]
If the M1 Operational Mode pin is also HIGH, the just previously written address.
EOM
bit is erased, and recording starts at that
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Good Audio Design Practices Winbond ChipCorder products are very high-quality single-chip voice recording and playback devices. To ensure the highest quality voice reproduction, it is important that good audio design practices on layout and power supply decoupling are followed. Please refer to Application Information Section of ChipCorder products in Winbond website (www.winbond-usa.com) for details.
Good Audio Design Practices (apin11.pdf) Single-Chip Board Layout Diagrams (apin12.pdf)
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8. TIMING DIAGRAMS
TCE CE P/R TSET THOLD PD A0-A8 MIC ANA IN OVF Don't Care Don't Care TSET TPUD TOVF Don't Care Don't Care TPDH TPDS TPDR
FIGURE 1: RECORD
TCE CE TSET P/R THOLD PD A0-A8 Don't Care Don't Care TSET SP+/OVF EOM TPUD TEOM TOVF Don't Care Don't Care TPDH TPDS TPDP
FIGURE 2: PLAYBACK
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Start CE
(Start/Pause)
Pause TCE TSET
Start TCE
Stop
TCE TSET
TSET
P/R PD
(Stop/Reset)
TSET TSET
TPD
TSET
A0-A8 MIC ANA IN OVF TRUN EOM
(Run)
Notes (1)
TPAUSE TDB
(4, 5)
TPUD
(2) (3)
TDB
TPUD
(6, 7)
TDB
(8)
FIGURE 3: PUSH-BUTTON MODE RECORD
Start CE
(Start/Pause)
Pause TCE TSET
Start
Stop
TCE TSET
TSET
P/R PD
(Stop/Reset)
TSET TSET
TPD
TSET
A0-A8 SP+/OVF TRUN EOM
(Run)
Notes (1)
TPAUSE TDB
(4, 5)
TPUD
(2) (3)
TDB
TPUD
(6, 7)
TDB
(8)
FIGURE 4: PUSH-BUTTON MODE PLAYBACK Publication Release Date: June 2003 Revision 1.0
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Notes for Push-Button modes: 1. 2. 3. 4. A8, A7, and A6 = 1 for push-button operation. The first CE LOW pulse performs a start function. The part will begin to play or record after a power-up delay TPUD. The part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of
CE and pause.
5. 6.
The second CE LOW pulse, and every even pulse thereafter, performs a Pause function. Again, the part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of CE , which would restart an operation. In addition, the part will not do an internal power down until CE is HIGH for the TDB time.
7. 8.
The third CE LOW pulse, and every odd pulse thereafter, performs a Resume function. At any time, a HIGH level on PD will stop the current function, reset the address counter, and power down the device.
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9. ABSOLUTE MAXIMUM RATINGS
TABLE 4: ABSOLUTE MAXIMUM RATINGS (DIE) CONDITIONS Junction temperature Storage temperature range Voltage applied to any pad Voltage applied to any pad (Input current limited to 20mA) VCC - VSS VALUES 150C -65C to +150C (VSS -0.3V) to (VCC +0.3V) (VSS -1.0V) to (VCC +1.0V) -0.3V to +7.0V
TABLE 5: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) CONDITIONS Junction temperature Storage temperature range Voltage applied to any pin Voltage applied to any pin (Input current limited to 20 mA) Lead temperature (Soldering - 10sec) VCC - VSS VALUES 150C -65C to +150C (VSS -0.3V) to (VCC +0.3V) (VSS -1.0V) to (VCC +1.0V) 300C -0.3V to +7.0V
Note:
Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability and performance. Functional operation is not implied at these conditions.
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9.1 OPERATING CONDITIONS
TABLE 6: OPERATING CONDITIONS (DIE) CONDITIONS Commercial operating temperature range Supply voltage (VCC) Ground voltage (VSS)
[1] [2]
VALUES 0C to +50C +4.5V to +6.5V 0V
TABLE 7: OPERATING CONDITIONS (PACKAGED PARTS) CONDITIONS Commercial operating temperature range Supply voltage (VCC) Ground voltage (VSS)
[1] [2] [3]
VALUES 0C to +70C +4.5V to +5.5V 0V
Notes:
[1] [2] [3]
VCC = VCCA = VCCD VSS = VSSA = VSSD Case Temperature
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10. ELECTRICAL CHARACTERISTICS
10.1. PARAMETERS FOR PACKAGED PARTS
TABLE 8: DC PARAMETERS - Packaged Parts PARAMETERS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
OVF Output High Voltage EOM Output High Voltage
SYMBOL
MIN [2] 2.0
TYP [1]
MAX [2] 0.8 0.4
UNITS V V V V V
CONDITIONS
VIL VIH VOL VOH VOH1 VOH2 ICC ISB IIL IILPD REXT RMIC RAUX RANA IN APRE1 APRE2 AAUX AARP RAGC 21 2.5 16 4 5 2.3 21 9 11 3 24 -15 0.98 23 5 VCC - 0.4 2.4 VCC - 1.0 VCC - 0.8 25 1
IOL = 4.0 mA IOH = -10 A IOH = -1.6 mA IOH = -3.2 mA REXT = [3]
[3]
V 30 10 1 130 mA A A A 15 20 5 26 5 1.0 26 9.5 K K K dB dB V/V dB K
VCC Current (Operating) VCC Current (Standby) Input Leakage Current Input Current HIGH w/Pull Down Output Load Impedance Preamp Input Resistance AUX IN Input Resistance ANA IN Input Resistance Preamp Gain 1 Preamp Gain 2 AUX IN/SP+ Gain ANA IN to SP+/- Gain AGC Output Resistance
Notes:
[1] [2]
Force VCC [4] Speaker Load MIC and MIC REF Pins
AGC = 0.0V AGC = 2.5V
Typical values @ TA = 25 and VCC = 5.0V. All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. VCCA and VCCD connected together. XCLK pin only.
[3] [4]
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
TABLE 9: AC PARAMETERS - Packaged Parts CHARACTERISTIC Sampling Frequency ISD2532 ISD2540 ISD2548 ISD2564 Filter Pass Band ISD2532 ISD2540 ISD2548 ISD2564 Record Duration ISD2532 ISD2540 ISD2548 ISD2564 Playback Duration ISD2532 ISD2540 ISD2548 ISD2564
CE Pulse Width
SYMBOL FS
MIN[2]
TYP[1] 8.0 6.4 5.3 4.0
MAX[2]
UNITS kHz kHz kHz kHz kHz kHz kHz kHz sec sec sec sec sec sec sec sec nsec nsec nsec msec msec msec msec
[7] [7] [7] [7]
CONDITIONS
FCF 3.4 2.7 2.3 1.7 TREC 32 40 48 64 TPLAY 32 40 48 64 TCE TSET THOLD TPUD 25.0 31.0 37.0 50.0 100 300 0
[7] [7] [7] [7] [7] [7] [7] [7]
3 dB Roll-Off Point [3][8] 3 dB Roll-Off Point [3][8] 3 dB Roll-Off Point [3][8] 3 dB Roll-Off Point [3][8]
Control/Address Setup Time Control/Address Hold Time Power-Up Delay ISD2532 ISD2540 ISD2548 ISD2564
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ISD2532/40/48/64
TABLE 9: AC PARAMETERS - Packaged Parts (Cont'd) CHARACTERISTIC
PD Pulse Width (record) ISD2532 ISD2540 ISD2548 ISD2564 PD Pulse Width (Play) ISD2532 ISD2540 ISD2548 ISD2564 PD Pulse Width (Static) Power Down Hold TPDS TPDH TEOM 12.5 15.625 18.75 25.0 TOVF THD POUT VOUT VIN1 VIN2 VIN3 6.5 1 12.2 2 50 2.5 20 50 1.25 msec msec msec msec sec % mW V p-p mV mV V @ 1 kHz REXT = 16
[4]
SYMBOL
TPDR
MIN[2]
TYP[1]
25.0 31.25 37.5 50.0
MAX[2]
UNITS
msec msec msec msec msec msec msec msec nsec nsec
[6]
CONDITIONS
TPDP 12.5 15.625 18.75 25.0 100 0
EOM Pulse Width
ISD2532 ISD2540 ISD2548 ISD2564 Overflow Pulse Width Total Harmonic Distortion Speaker Output Power Voltage Across Speaker Pins MIC Input Voltage ANA IN Input Voltage AUX Input Voltage
Notes:
[1] [2] [3] [4] [5] [6] [7]
REXT = 600 , Aux In=1.25Vp-p
Peak-to-Peak Peak-to-Peak
[5]
Peak-to-Peak; REXT = 16
Typical values @ TA = 25C, VCC = 5.0V and timing measured at 50% levels. All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions) From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT = 12.2 mW, typical. With 5.1 K series resistor at ANA IN. TPDS is required during a static condition, typically overflow. Sampling Frequency and Duration can vary as much as 2.25 percent over the commercial temperature range. For greater stability, an external clock can be utilized (see Pin Descriptions) Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to output, expect a 6 dB drop by nature of passing through both filters.
[8]
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
10.1.1. Typical Parameter Variation with Voltage and Temperature - Packaged Parts
25
Operating Current (mA)
Chart 1: Record Mode Operating Current (ICC)
Standby Current (mA)
Chart 3: Standby Current (ISB) 1.2 1.0 0.8 0.6 0.4 0.2 0
20 15 10 5 0 -40 25 70 85
Temperature (C) 5.5 Volts 4.5 Volts
-40
25
70
85
Temperature (C) 5.5 Volts 4.5 Volts
Chart 2: Total Harmonic Distortion 0.7
Percent Distortion (%)
Chart 4: Oscillator Stability 0.4
Percent Change (%)
0.6 0.5 0.4 0.3 0.2 0.1 0 -40 25 70 85
Temperature (C) 5.5 Volts 4.5 Volts
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 25 70 85
Temperature (C) 5.5 Volts 4.5 Volts
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ISD2532/40/48/64
10.2. PARAMETERS FOR DIE
TABLE 10: DC PARAMETERS - Die PARAMETERS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
OVF Output High Voltage EOM Output High Voltage
SYMBOL
MIN[2] 2.0
TYP[1]
MAX[2] 0.8 0.4
UNITS V V V V V
CONDITIONS
VIL VIH VOL VOH VOH1 VOH2 ICC ISB IIL IILPD REXT RMIC RAUX RANA IN APRE1 APRE2 AAUX AARP RAGC 21 2.5 16 4 5 2.3 21 9 11 3 24 -15 0.98 23 5 VCC - 0.4 2.4 VCC - 1.0 VCC 0.8 25 1
IOL = 4.0 mA IOH = -10 A IOH = -1.6 mA IOH = -3.2 mA REXT = [3]
[2]
V 30 10 1 130 mA A A A 15 20 5 26 5 1.0 26 9.5 K K K dB dB V/V dB K
VCC Current (Operating) VCC Current (Standby) Input Leakage Current Input Current HIGH w/Pull Down Output Load Impedance Preamp IN Input Resistance AUX IN Input Resistance ANA IN Input Resistance Preamp Gain 1 Preamp Gain 2 AUX IN/SP+ Gain ANA IN to SP+/- Gain AGC Output Resistance
Notes:
[1] [2]
Force VCC [4] Speaker Load MIC and MIC REF Pads
AGC = 0.0V AGC = 2.5V
Typical values @ TA = 25C and VCC = 5.0V. All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. VCCA and VCCD connected together. XCLK pad only.
[3] [4]
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
TABLE 11: AC PARAMETERS - Die CHARACTERISTIC Sampling Frequency ISD2532 ISD2540 ISD2548 ISD2564 Filter Pass Band ISD2532 ISD2540 ISD2548 ISD2564 Record Duration ISD2532 ISD2540 ISD2548 ISD2564 Playback Duration ISD2532 ISD2540 ISD2548 ISD2564
CE Pulse Width
SYMBOL FS
MIN[2]
TYP[1] 8.0 6.4 5.3 4.0
MAX[2]
UNITS kHz kHz kHz kHz kHz kHz kHz kHz sec sec sec sec sec sec sec sec nsec nsec nsec msec msec msec msec
[7] [7] [7] [7]
CONDITIONS
FCF 3.4 2.7 2.3 1.7 TREC 32 40 48 64 TPLAY 32 40 48 64 TCE TSET THOLD TPUD 25.0 31.3 37.5 50.0 100 300 0
[7] [7] [7] [7] [7] [7] [7] [7]
3 dB Roll-Off Point [3][8] 3 dB Roll-Off Point [3][8] 3 dB Roll-Off Point [3][8] 3 dB Roll-Off Point [3][8]
Control/Address Setup Time Control/Address Hold Time Power-Up Delay ISD2532 ISD2540 ISD2548 ISD2564
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ISD2532/40/48/64
TABLE 11: AC PARAMETERS - Die (Cont'd) CHARACTERISTIC
PD Pulse Width (Record) ISD2532 ISD2540 ISD2548 ISD2564 PD Pulse Width (Play) ISD2532 ISD2540 ISD2548 ISD2564 PD Pulse Width (Static) Power Down Hold TPDS TPDH TEOM 12.5 15.625 18.75 25.0 TOVF THD POUT VOUT VIN1 VIN2 VIN3 6.5 1 12.2 2 50 2.5 20 50 1.25 msec msec msec msec sec % mW V p-p mV mV V @ 1 kHz REXT = 16
[4]
SYMBOL
TPDR
MIN[2]
TYP[1]
25.0 31.25 37.5 50.0
MAX[2]
UNITS
msec msec msec msec
CONDITIONS
TPDP 12.5 15.625 18.75 25.0 100 0 msec msec msec msec nsec nsec
[6]
EOM Pulse Width
ISD2532 ISD2540 ISD2548 ISD2564 Overflow Pulse Width Total Harmonic Distortion Speaker Output Power Voltage Across Speaker Pins MIC Input Voltage ANA IN Input Voltage AUX Input Voltage
Notes:
[1] [2] [3] [4] [5] [6] [7]
REXT=600 , Aux In=1.25Vp-p
Peak-to-Peak Peak-to-Peak
[5]
Peak-to-Peak; REXT = 16
Typical values @ TA = 25C, VCC = 5.0V and timing measured at 50% levels. All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions) From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT = 12.2 mW, typical. With 5.1 K series resistor at ANA IN. TPDS is required during a static condition, typically overflow. Sampling Frequency and playback Duration can vary as much as 2.25 percent over the commercial temperature range. For greater stability, an external clock can be utilized (see Pin Descriptions) Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to output, expect a 6 dB drop by nature of passing through both filters.
[8]
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
10.2.1. Typical Parameter Variation with Voltage and Temperature - Die
30
Operating Current (mA)
Chart 5: Record Mode Operating Current (ICC)
Standby Current (mA)
Chart 7: Standby Current (ISB) 1.0 0.8 0.6 0.4 0.2 0
25 20 15 10 5 0 -40 25
Temperature (C) 6.5 Volts 5.5 Volts 4.5 Volts
50
-40
25
Temperature (C)
50
6.5 Volts
5.5 Volts
4.5 Volts
Chart 6: Total Harmonic Distortion 0.7
Percent Distortion (%)
Chart 8: Oscillator Stability 0.2
Percent Change (%)
0.6 0.5 0.4 0.3 0.2 0.1 0 -40 25
Temperature (C) 6.5 Volts 5.5 Volts 4.5 Volts
0 -0.2 -0.4 -0.6 -0.8 -1.0
50
-40
25
Temperature (C)
50
6.5 Volts
5.5 Volts
4.5 Volts
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ISD2532/40/48/64
10.3. PARAMETERS FOR PUSH-BUTTON MODE
TABLE 12: PARAMETERS FOR PUSH-BUTTON MODE PARAMETERS
CE Pulse Width (Start/Pause)
SYMBOL TCE TSET TPUD
MIN[2]
TYP[1] 300 300 25.0 31.25 37.25 50.0
MAX[2]
UNITS nsec nsec msec msec msec msec nsec
CONDITIONS
Control/Address Setup Time Power-Up Delay ISD2532 ISD2540 ISD2548 ISD2564 PD Pulse Width (Stop/Restart)
CE to EOM HIGH CE to EOM LOW CE HIGH Debounce
TPD TRUN TPAUSE TDB 70 85 105 135 25 50
300 400 400
nsec nsec
ISD2532 ISD2540 ISD2548 ISD2564
Notes:
[1] [2]
105 135 160 215
msec msec msec msec
Typical values @ TA = 25C, VCC = 5.0V and timing measured at 50% levels. All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested.
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
11. TYPICAL APPLICATION CIRCUIT
VCC
ISD2532/40/48/64 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6
POWER DOWN
VCCD 28 VCCA 16 C6 0.1 F VSSD 12 VSSA 13 SP+ 14 SP- 15 AUX IN 11 ANA IN 20 ANA OUT 21 MIC REF 18 MIC 17 AGC 19 R1 1 K R2 470 K C2 4.7 F C4 220
16 SPEAKER
VCC
VSS R4 100 K
C7 0.1 F
C8 22
F
CHIP ENABLE
9 A7 10 A8 23 CE 24 PD 27 P/R 25 OEM 22 OVF 26 XCLK
R6 5.1 K (Note) VCC
C3 0.1 F
PLAYBACK/RECORD
C1 0.1 F R3 10 K
C5 0.1 F
F
ELECTRET MICROPHONE
R5 10 K
FIGURE 5: DESIGN SCHEMATIC
Note: If desired, pin 18 (PDIP package) may be left unconnected (microphone preamplifier noise will be higher). In this case, pin 18 must not be tied to any other signal or voltage. Additional design example schematics are provided below.
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ISD2532/40/48/64
TABLE 13: APPLICATION EXAMPLE - BASIC DEVICE CONTROL Control Step 1 2 3A 3B 4A 4B Function Power up chip and select Record/Playback Mode Set message address for record/playback Begin playback Begin record End playback End record Action 1. PD = LOW, 2. P/ R = As desired Set addresses A0-A8 P/ R = HIGH, CE = Pulse LOW P/ R = LOW, CE = LOW Automatic PD or CE = HIGH
TABLE 14: APPLICATION EXAMPLE - PASSIVE COMPONENT FUNCTIONS Parts R1 R2 R3, R5 R4 R6 C1, C5 Function Microphone power supply decoupling Release time constant Microphone biasing resistors Series limiting resistor Series limiting resistor Microphone DC-blocking capacitor Lowfrequency cutoff Attack/Release time constant Low-frequency cutoff capacitor Microphone power supply decoupling Power supply capacitors Comments Reduces power supply noise Sets release time for AGC Provides biasing for microphone operation Reduces level to prevent distortion at higher supply voltages Reduces level to high supply voltages Decouples microphone bias from chip. Provides single-pole low-frequency cutoff and command mode noise rejection. Sets attack/release time for AGC Provides additional pole for low-frequency cutoff Reduces power supply noise Filter and bypass of power supply
C2 C3 C4 C6, C7, C8
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
VCC
S1
MC68HC705K1A OSC1 OSC2 RESET IRQ PB0 PB1 PA0 PA1 PA2 PA3 PA4 VDD VSS PA5 PA6 PA7
S2 PLAY
S3 MSG#
D1 RUN
ISD2532/40/48/64 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 9 A7 10 A8 23 CE 24 PD 27 P/R 25 OEM 22 OVF 26 XCLK VCCD 28 VCCA 16 VSSD 12 VSSA 13 SP+ 14 SP- 15 AUX IN 11 ANA IN 20 ANA OUT 21 MIC REF 18 MIC 17 AGC 19
RECORD
R1 TBD
U1
U2
FIGURE 6: ISD2532/40/48/64 APPLICATION EXAMPLE - MICROCONTROLLER/ISD2500 INTERFACE
In this simplified block diagram of a microcontroller application, the Push-Button Mode and message cueing are used. The microcontroller is a 16-pin version with enough port pins for buttons, an LED, and the ISD2500 series device. The software can be written to use three buttons: one each for play and record, and one for message selection. Because the microcontroller is interpreting the buttons and commanding the ISD2500 device, software can be written for any function desired in a particular application. Note: Winbond does not recommend connecting address lines directly to a microprocessor bus. Address lines should be externally latched.
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ISD2532/40/48/64
ISD2532/40/48/64 VCC 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 9 A7 10 A8 23 CE 24 PD 27 P/R 25 OEM
PLAYBACK/RECORD
VCC
VCCD 28 VCCA 16 C4 0.1 F VSSD 12 VSSA 13 SP+ 14 SP- 15 AUX IN 11 ANA IN 20 ANA OUT 21 MIC REF 18 MIC 17 AGC 19 R1 1 K R2 470 K C2 4.7
16 SPEAKER
VCC R6 100 K R7 100 K
VSS
C1 0.1 F
C5 22
F
VCC
START/PAUSE
STOP/RESET
R4 5.1 K (Note)
C3 0.1 F
22 OVF 26 XCLK
VCC
C1 0.1 F R3 10 K C4 220
C5 0.1 F
F
F
ELECTRET MICROPHONE
R5 10 K
FIGURE 7: ISD2532/40/48/64 APPLICATION EXAMPLE - PUSH-BUTTON
Note: Please refer to page 13 for more details.
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
TABLE 15: APPLICATION EXAMPLE - PUSH-BUTTON CONTROL Control Step 1 2A 2B 3 4A 4B Function Select Record/Playback Mode Begin playback Begin record Pause record or playback End playback End record P/ R = As desired P/ R = HIGH, CE = Pulse LOW P/ R = LOW, CE = Pulse LOW
CE = Pulsed LOW
Action
Automatic at EOM marker or PD = Pulsed HIGH PD = Pulsed HIGH
TABLE 16: APPLICATION EXAMPLE - PASSIVE COMPONENT FUNCTIONS Parts R2 R4 R6, R7 C1, C4, C5 C2 C3 Function Release time constant Series limiting resistor Pull-up and pull-down resistors Power supply capacitors Attack/Release time constant Low-frequency cutoff capacitor Comments Sets release time for AGC Reduces level to prevent distortion at higher supply voltages Defines static state of inputs Filters and bypass of power supply Sets attack/release time for AGC Provides additional pole for low-frequency cutoff
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ISD2532/40/48/64
12. PACKAGE DRAWING AND DIMENSIONS
12.1. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE IC (SOIC)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1
2345
6 7 8 9 10 11 12 13 14
A
G C
B D E
F
H
INCHES Min A B C D E F G H 0.400 0.024 0.701 0.097 0.292 0.005 0.014 Nom 0.706 0.101 0.296 0.009 0.016 0.050 0.406 0.032 0.410 0.040 10.16 0.61 Max 0.711 0.104 0.299 0.0115 0.019 Min 17.81 2.46 7.42 0.127 0.35
MILLIMETERS Nom 17.93 2.56 7.52 0.22 0.41 1.27 10.31 0.81 10.41 1.02 Max 18.06 2.64 7.59 0.29 0.48
Note: Lead coplanarity to be within 0.004 inches.
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
12.2. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP)
INCHES Min A B1 B2 C1 C2 D D1 E F G H J S q 0.008 0.070 0 0.015 0.125 0.015 0.055 0.018 0.060 0.100 0.010 0.075 0.012 0.080 15 0.20 1.78 0 0.135 0.022 0.065 0.065 0.600 0.530 0.540 1.445 Nom 1.450 0.150 0.070 0.075 0.625 0.550 0.19 0.38 3.18 0.38 1.40 1.65 15.24 13.46 Max 1.455 Min 36.70
MILLIMETERS Nom 36.83 3.81 1.78 13.72 1.91 15.88 13.97 4.83 3.43 0.46 1.52 2.54 0.25 1.91 0.30 2.03 15 0.56 1.62 Max 36.96
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ISD2532/40/48/64
12.3. 28-LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1
A A B B
1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15
G G F C
E E D H H I J J
Plastic Thin Small Outline Package (TSOP) Type 1 Dimensions INCHES M in A B C D E F G H I J Note: 0.037 0 0.020 0.004
0
M ILLIM ETERS M ax 0.535 0.469 0.319 0.006 0.011 0.041 6 0.028 0.008
0
Nom 0.528 0.465 0.315 0.009 0.0217 0.039 3 0.022
0
M in 13.20 11.70 7.90 0.05 0.17 0.95 0 0.50 0.10
0
Nom 13.40 11.80 8.00 0.22 0.55 1.00 3 0.55
0
M ax 13.60 11.90 8.10 0.15 0.27 1.05 6 0.70 0.21
0
0.520 0.461 0.311 0.002 0.007
Lead coplanarity to be within 0.004 inches.
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
12.4. DIE BONDING PHYSICAL LAYOUT [1]
A3 A1 A2 A0 VCCD XCLK P/R EOM PD
ISD2532/40/48/64 o Die Dimensions X: 149.6 + 1 mils Y: 206.3 + 1 mils o Die Thickness [2] 11.8 + .4 mils o Pad Opening 111 microns (4.4 mils)
A4 A5 A6
CE OVF
ISD2532/40/48/64
NC A7 A8 AUX IN VSSD VSSA SP+ SPMIC AGC
ANA OUT ANA IN
VCCA MIC REF
Notes:
[1]
The backside of die is internally connected to VSS. It MUST NOT be connected to any other potential or damage may occur. Die thickness is subject to change, please contact Winbond factory for status and availability.
[2]
- 38 -
ISD2532/40/48/64
ISD2532/40/48/64 PRODUCT PAD DESIGNATIONS
(with respect to die center) Pad
OVF CE
Pad Name Overflow Output Chip Enable Input Power Down Input End of Message No Connect (optional) Playback/Record VCC Digital Power Supply Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 NC Address 7 Address 8 Auxiliary Input VSS Digital Power Supply VSS Analog Power Supply Speaker Output + Speaker Output VCC Analog Power Supply Microphone Input Microphone Reference Automatic Gain Control Analog Input Analog Output
X Axis (m) 1675.95 1728.08 1731.83 1342.20 987.83 808.58 546.08 -896.55 -1114.05 -1329.68 -1542.68 -1639.05 -1696.80 -1696.80 -1729.80 -1729.80 -1729.80 -1408.80 -1111.43 -406.43 -46.05 388.20 747.83 1102.58 1296.08 1667.70 1729.95 1702.20
Y Axis (m) 1779.38 2114.25 2383.88 2411.63 2450.63 2453.25 2449.13 2425.13 2425.13 2425.13 2425.13 2178.75 1960.88 1731.38 -1875.75 -2061.00 -2343.38 -2408.25 -2388.75 -2431.13 -2360.25 -2360.25 -2403.00 -2438.63 -2438.63 -2422.88 -1946.63 -1703.63
PD
EOM
XCLK P/ R VCCD A0 A1 A2 A3 A4 A5 A6 NC A7 A8 AUX IN VSSD VSSA SP+ SPVCCA MIC MIC REF AGC ANA IN ANA OUT
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
13. ORDERING INFORMATION Product Number Descriptor Key
ISD2 5
ISD2500 Series Duration: 32 40 48 64 = = = = 32 seconds 40 seconds 48 seconds 64 seconds S= Special Temperature Field: Blank = Commercial Packaged (0C to +70C) or Commercial Die (0C to +50C) Package Type: P= 28-Lead 600mil Plastic Dual Inline Package (PDIP) 28-Lead 300mil Small Outline Integrated Circuit (SOIC) 28-Lead 8x13.4 mm Thin Small Outline Package (TSOP) Type 1
E=
X = Die
When ordering ISD2532/40/48/64 products refer to the following part numbers which are supported in volume for this product series. Consult the local Winbond Sales Representative or Distributor for availability information. Part Number ISD2532P ISD2532S ISD2532E ISD2532X Part Number ISD2540P ISD2540S ISD2540E ISD2540X ISD2548E ISD2548X ISD2564X Part Number ISD2548P Part Number ISD2564P
For the latest product information, access Winbond's worldwide website at http://www.winbond-usa.com
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ISD2532/40/48/64
14. VERSION HISTORY
VERSION 0 1.0 DATE Apr. 1998 Jun. 2003 DESCRIPTION Preliminary Specifications. Reformat the document. Update TSOP description in pin configuration section. Revise Table 1: Product Summary. Update TSOP and SOIC package option. Remove industrial temperature option.
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Publication Release Date: June 2003 Revision 1.0
ISD2532/40/48/64
The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental injury could occur. Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Winbond makes no representation or warranty that such applications shall be suitable for the use specified. ISD(R) and ChipCorder(R) are trademarks of Winbond Electronics Corporation. The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond.
(R) (R) Information contained in this ISD ChipCorder data sheet supersedes all data for the ISD ChipCorder products (R) published by ISD prior to August, 1998.
This data sheet and any future addendum to this data sheet is(are) the complete and controlling ISD ChipCorder product specifications. In the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety.
(R)
(R)
Copyright(c) 2003, Winbond Electronics Corporation. All rights reserved. ISD(R) is a registered trademark of Winbond. ChipCorder(R) is a trademark of Winbond. All other trademarks are properties of their respective owners.
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441797 http://www.winbond-usa.com/
Winbond Electronics (Shanghai) Ltd.
27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998
Taipei Office
9F, No. 480, Pueiguang Rd. Neihu District Taipei, 114 Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG. 3-7-18 Shinyokohama Kohokuku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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